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Agilent HDMP-0482 Octal Cell Port Bypass Circuit
with CDR and Data Valid Detection Data Sheet
Features * Supports 1.0625 GBd fibre channel operation * Supports 1.25 GBd Gigabit Ethernet (GE) operation * Octal cell PBC/CDR in one package * CDR location determined by choice of cable input/output * Amplitude valid detection on FM_NODE[7] input * Data valid detection on FM_NODE[0] input - Run length violation detection - Comma detection - Configurable for both singleframe and multi-frame detection * Equalizers on all inputs * High speed LVPECL I/O * Buffered Line Logic (BLL) outputs (no external bias resistors required) * 1.09 W typical power at Vcc=3.3V * 64 Pin, 14 mm, low cost plastic QFP package Applications * RAID, JBOD, BTS cabinets * Four 2:1 muxes * Four 1:2 buffers * 1 = > N gigabit serial buffer * N = > 1 gigabit serial mux
Description The HDMP-0482 is an Octal Cell Port Bypass Circuit (PBC) with Clock and Data Recovery (CDR) and data valid detection capability included. This device minimizes part count, cost and jitter accumulation while repeating incoming signals. Port Bypass Circuits are used in hard disk arrays constructed in Fibre Channel Arbitrated Loop (FC-AL) configurations. By using Port Bypass Circuits, hard disks may be pulled out or swapped while other disks in the array are available to the system. A Port Bypass Circuit (PBC) consists of multiple 2:1 multiplexers daisy chained along with a CDR. Each port has two modes of operation: "disk in loop" and "disk bypassed". When the "disk in loop" mode is selected, the loop goes into and out of the disk drive at that port. For example, data goes from the HDMP-0482's TO_NODE[n] differential output pins to the Disk Drive Transceiver IC's (e.g. an HDMP-1636A) Rx differential input pins. Data from the Disk Drive Transceiver IC's Tx differential outputs goes to
the HDMP-0482's FM_NODE[n] differential input pins. When the "disk bypassed" mode is selected, the disk drive is either absent or non-functional and the loop bypasses the hard disk. The "disk bypassed" mode is enabled by pulling the BYPASS[n]pin low. Leave BYPASS[n]floating to enable the "disk in loop" mode. HDMP-0482's may be cascaded with other members of the HDMP-04XX/HDMP-05XX family through the FM_NODE and TO_NODE pins to accommodate any number of hard disks. The unused cells in this PBC may be bypassed by using pulldown resistors on the BYPASS[n]- pins for these cells. An HDMP-0482 may also be used as eight 1:1 buffers, one with a CDR and seven without. For example, an HDMP-0482 may be placed in front of a CMOS ASIC to clean the jitter of the outgoing signal (CDR path) and to better read the incoming signal (nonCDR path). In addition, the HDMP-0482 may be configured as four 2:1 multiplexers or as four 1:2 buffers.
HDMP-0482
CAUTION: As with all semiconductor ICs, it is advised that normal static precautions be taken in the handling and assembly of this component to prevent damage and/or degradation which may be induced by electrostatic discharge (ESD).
The HDMP-0482 design allows for CDR placement at any location with respect to the hard disk slots. For example, if the BYPASS[0]- pin is floating and hard disk slots A to G are connected to PBC cells 1 to 7, respectively, the CDR function will be performed
before entering the hard disk at slot A. To obtain a CDR function after slot G, BYPASS[1]- must be floating and hard disk slots A to G must be connected to PBC cells 2,3,4,5,6,7 and 0, respectively. Table 1 shows all possible connections.
For configurations where the CDR is before slot A, a Data Valid (FM_NODE[0]_DV) pin indicates whether the incoming data on FM_NODE[0] is valid Fibre Channel data. In addition, an Amplitude Valid (FM_NODE[7]AV) pin shows the status of the signal at FM_NODE[7].
7 0
FM_NODE(7)_AV
AV
1
BYPASS1
2
BYPASS2
3
BYPASS3
4
BYPASS4
5
BYPASS5
6
BYPASS6
1 0
1 0
1 0
1 0
1 0
1 0
1 0
BYPASS7
1 0
0 1 FM_NODE[0]_DV DV CDR
MODE_VDD BYPASS0
FSEL
REFCLK RFCM
MODE_VDD BYPASS0
Figure 1. Block Diagram of HDMP-0482.
HDMP-0482 Block Diagram
CDR The Clock and Data Recovery (CDR) block is responsible for frequency and phase locking onto the incoming serial data stream and resampling the incoming data based on the recovered clock. An automatic locking feature allows the CDR to lock onto the input data stream without external training controls. It does this by continually frequency locking onto the 106.25 MHz reference clock (REFCLK) and then phase locking onto the input data stream. Once bit locked, the CDR generates a high-speed sampling clock. This clock is used to sample or repeat the incoming data to produce the CDR output. The CDR jitter specifications listed in this data sheet assume an input that has been 8B/10B encoded. DV Output The Data Valid (DV) block detects if the incoming data on FM_NODE[0] is valid Fibre Channel data. The DV checks for sufficient K28.5+ characters (per Fibre Channel framing rules) and for run length violations (per 8B/ 10B encoding) on the data coming out of the CDR. The FM_NODE[0]_DV output is pulled low if a run length violation (RLV) occurs, or if there are no commas detected (NCD) in a sufficient time. It is pulled high if no errors are found. A RLV error is defined as any consecutive sequence of 1s or 0s greater than five in the serial data bit stream. A NCD error indicates the absence of a seven-bit pattern (0011111) present in the positive disparity comma (K28.5+) character. A K28.5+ character should occur at the beginning of every Fibre Channel frame of 2148 bytes (or 21480 serial bits), as well as many times within and between frames. If this seven-bit pattern is not found within a 215 bit (~31 s) interval, an NCD error is generated.
2
When the DV is configured in single-frame mode (FSEL low), any RLV and NCD errors stored during this 215 bit interval cause FM_NODE[0]_DV to be pulled low on the next subsequent interval. FM_NODE[0]_DV remains low until after an entire 215 bit interval in which no RLVs occur and at least one comma is detected. At that time, FM_NODE[0]_DV is pulled high. A multi-frame mode (FSEL high) configuration of the DV is also available. When in multi-frame mode, the FM_NODE[0]_DV output is only pulled low when four consecutive 215 bit intervals of bad data have been transmitted. Once low, FM_NODE[0]_DV does not go high again until four consecutive 215 bit intervals of good data are transmitted. AV Output The Amplitude Valid (AV) block detects if the incoming data on FM_NODE[7] is valid by examining the differential amplitude of that input. The incoming data is considered valid, and FM_NODE[7]_AV is driven high, as long as the amplitude is greater than 400 mV (differential peak-to-peak). FM_NODE[7]_AV is driven low as long as the amplitude of the input signal is less than 100 mV (differential peak-to-peak). When the amplitude of the input signal is between 100- 400 mV (differential peak-to-peak), FM_NODE[7]_AV is unpredictable. The FM_NODE[7]_AV output is latched in with an internally generated 215 bit clock. Similar to the DV function, the AV can be configured for single-frame or multi-frame operation.
BLL Output All TO_NODE[n] high-speed differential outputs are driven by a Buffered Line Logic (BLL) circuit that has on-chip source termination, so no external bias resistors are required. The BLL Outputs on the HDMP-0482 are of equal strength and can drive in excess of 120 inches of FR-4 PCB trace. Unused outputs should not be left unconnected. Ideally, unused outputs should have their differential pins shorted together with a short PCB trace. If transmission lines are connected to the output pins, the lines should be differentially terminated with an appropriate resistor. The value of the termination resistor should match the PCB trace differential impedance. EQU Input All FM_NODE[n] high-speed differential inputs have an Equalization (EQU) buffer to offset the effects of skin loss and dispersion on PCBs. An external termination resistor is required across all high-speed inputs. BYPASS[N]- Input The active low BYPASS[n]- inputs control the data flow through the HDMP-0482. All BYPASS pins are LVTTL and contain internal pullup circuitry. To bypass a port, the appropriate BYPASS[n]- pin should be connected to GND through a 1k resistor. Otherwise, the BYPASS[n]- inputs should be left to float. In this case, the internal pull-up circuitry will force them high.
REFCLK Input The LVTTL REFCLK input provides a reference oscillator for frequency acquisition of the CDR. The REFCLK frequency should be within 100 ppm of one-tenth or one-twentieth of the incoming data rate in baud (106.25 MHz 100 ppm, or 53.125 MHz 100 ppm for FC-AL running at 1.0625 GBd). RFCM Input The LVTTL RFCM input configures the CDR to accept a REFCLK at either one-tenth or one-twentieth of the incoming data rate in baud. The RFCM input has internal pull-up circuitry, so the user should connect the pin to GND through a 1k resistor for a REFCLK at one-twentieth the incoming data rate. For a REFCLK at one-tenth the incoming data rate, let RFCM float high. MODE_VDD Input The active high valid data detect mode pin selects data checking of the FM_NODE [0] +/- inputs. When high, MODE_VDD overides BYPASS [0] and forces the incoming data into the CDR for error checking. When low, the chip can be configured for CDR anywhere capability. Refer to Figures 2 & 3 for high and low MODE_VDD configuration.
3
1
BYPASS1
2
BYPASS2
3
BYPASS3
4
BYPASS4
5
BYPASS5
6
BYPASS6
7
BYPASS7
0
FM_NODE(7)_AV FM_NODE(7)_AV
AV
1 0
1 0
1 0
1 0
1 0
1 0
1 0
0 1 FM_NODE[0]_DV BYPASS0
Figure 2. Block Diagram of HDMP-0482, MODE_VDD is HIGH.
CDR DV
1
BYPASS1
2
BYPASS2
3
BYPASS3
4
BYPASS4
5
BYPASS5
6
BYPASS6
7
BYPASS7
0
AV
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
CDR FM_NODE[0]_DV DV
Figure 3. Block Diagram of HDMP-0482, MODE_VDD is LOW.
4
BYPASS0
Table 1. Pin Connection Diagram to Achieve Desired CDR Location.
Hard Disk Connection to PBC Cell CDR Position (x) Cell Connection to Cable ABCDEFG 1234567 xA B C D E F G 0 ABCDEFG 01234567 AxB C D E F G 7 ABCDEFG 01234567 A BxC D E F G 6 ABCDEFG 01234 A B CxD E F G 5
Hard Disk Connection to PBC Cell CDR Position (x) Cell Connection to Cable
ABCDEFG 5670123 A B C DxE F G 4
ABCDEFG 4567012 A B C D ExF G 3
ABCDEFG 3456701 A B C D E FxG 2
ABCDEFG 2345670 A B C D E F Gx 1
x denotes CDR position with respect to hard disks.
FM_NODE[7]+ FM_NODE[6]+ FM_NODE[5]+ TO_NODE[7]+ TO_NODE[6]+ FM_NODE[7]FM_NODE[6]FM_NODE[5]TO_NODE[7]TO_NODE[6]-
BYPASS[6]-
BYPASS[7]REFCLK RFCM FM_NODE[0]_DV VCC GND MODE_VDD VCCA GND CPLL1 CPLL0 FSEL BYPASS[0]FM_NODE[7]_AV FM_NODE[0]FM_NODE[0]+
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 40 9 39 10 38 11 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
BYPASS[5]-
VCCHS
GND
GND
VCC
VCCHS TO_NODE[5]+ TO_NODE[5]VCCHS TO_NODE[4]+ TO_NODE[4]BYPASS[4]FM_NODE[4]+ FM_NODE[4]GND FM_NODE[3]+ FM_NODE[3]BYPASS[3]TO_NODE[3]+ TO_NODE[3]VCCHS
Agilent
HDMP-0482
nnnn-nnn Rz.zz S YYWW
Figure 4. HDMP-0482 Package Layout and Marking, Top View. nnnn-nnn = wafer lot - build number; Rz.zz = Die Revision; S = Supplier Code; YYWW = Date Code (YY = year, WW = work week); COUNTRY = country of manufacture (on back side).
Table 2. I/O Type Definitions. I/O Type
I-LVTTL O-LVTTL HS_OUT HS_IN C S
Definition
LVTTL Input LVTTL Output High Speed Output, LVPECL Compatible High Speed Input External circuit node Power supply or ground
VCC
GND
TO_NODE[0]-
TO_NODE[0]+
VCCHS
TO_NODE[1]-
TO_NODE[1]+
BYPASS[1]-
FM_NODE[1]-
FM_NODE[1]+
VCC
FM_NODE[2]-
FM_NODE[2]+
BYPASS[2]-
TO_NODE[2]-
TO_NODE[2]+
5
Table 3. Pin Definitions for HDMP-0482. Pin Name
TO_NODE[0]+ TO_NODE[0]TO_NODE[1]+ TO_NODE[1]TO_NODE[2]+ TO_NODE[2]TO_NODE[3]+ TO_NODE[3]TO_NODE[4]+ TO_NODE[4]TO_NODE[5]+ TO_NODE[5]TO_NODE[6]+ TO_NODE[6]TO_NODE[7]+ TO_NODE[7]FM_NODE[0]+ FM_NODE[0]FM_NODE[1]+ FM_NODE[1]FM_NODE[2]+ FM_NODE[2]FM_NODE[3]+ FM_NODE[3]FM_NODE[4]+ FM_NODE[4]FM_NODE[5]+ FM_NODE[5]FM_NODE[6]+ FM_NODE[6]FM_NODE[7]+ FM_NODE[7]BYPASS[0]BYPASS[1]BYPASS[2]BYPASS[3]BYPASS[4]BYPASS[5]BYPASS[6]BYPASS[7]REFCLK CPLL1 CPLL0 FM_NODE[7]_AV
Pin
20 19 23 22 32 31 35 34 44 43 47 46 57 56 60 59 16 15 26 25 29 28 38 37 41 40 51 50 54 53 63 62 13 24 30 36 42 49 55 1 2 10 11 14
Pin Type
HS_OUT
Pin Description
Serial Data Outputs: High-speed outputs to a hard disk drive or to a cable input.
HS_IN
Serial Data Inputs: High-speed inputs from a hard disk drive or from a cable output.
I-LVTTL
Bypass Inputs: For "disk bypassed" mode, connect BYPASS[n]- to GND through a1k resistor. For "disk in loop" mode, float HIGH.
I-LVTTL C O-LVTTL
Reference Clock: A user-supplied clock reference used for frequency acquisition in the Clock and Data Recovery (CDR) circuit. Loop Filter Capacitor: A loop filter capacitor for the internal Clock and Data Recovery (CDR) circuit must be connected across the CPLL1 and CPLL0 pins. Recommended value is 0.1 F. Amplitude Valid: Indicates acceptable signal amplitude on the FM_NODE[7] inputs. If (FM_NODE[7]+ - FM_NODE[7]-) >= 400 mV peak-to-peak, FM_NODE[7]_AV = 1 If 400 mV > (FM_NODE[7]+ - FM_NODE[7]-) > 100 mV, FM_NODE[7]_AV = unpredictable If 100 mV >= (FM_NODE[7]+ - FM_NODE[7]-), FM_NODE[7]_AV = 0 Data Valid: Indicates valid Fibre Channel Data on the FM_NODE[0] inputs when HIGH. Indicates either run length violation error or no comma detected when LOW. Reference Clock Mode: To configure a one-twentieth-rate reference clock, connect RFCM to GND through a 1k resistor. To configure a one-tenth-rate reference clock, float RFCM HIGH. Valid Data Detect Mode: To allow data valid detection, float MODE_VDD HIGH. To configure chip for "CDR anywhere" capability, connect MODE_VDD to GND through a 1k resistor. Frame Select: To configure single-frame operation of the data valid and amplitude valid detection circuits, connect FSEL to GND through a 1k resistor. To configure multi-frame (4-frame) operation of the data valid and amplitude valid detection circuits, float FSEL HIGH.
FM_NODE[0]_DV RFCM MODE_VDD FSEL
4 3 7 12
O-LVTTL I-LVTTL I_LVTTL I_LVTTL
Table 3 is continued on next page. 6
Table 3, continued. Pin Definitions for HDMP-0482. Pin Name
GND
Pin
6 9 18 39 52 61 8 21 33 45 48 58 5 17 27 64
Pin Type
S
Pin Description
Ground: Normally 0 volts. See Figure 11 for Recommended Power Supply Filtering.
VCCA VCCHS[0,1] VCCHS[2,3] VCCHS[4] VCCHS[5] VCCHS[6,7] VCC
S S S S S S S S S S
Analog Power Supply: Normally 3.3 volts. Used to provide a clean supply line for the Clock and Data Recovery (CDR) circuit. See Figure 11 for Recommended Power Supply Filtering. High Speed Supply: Normally 3.3 volts. Used only for high-speed outputs (TO_NODE[n]). See Figure 11 for Recommended Power Supply Filtering.
Logic Power Supply: Normally 3.3 volts. Used for internal logic. See Figure 11 for Recommended Power Supply Filtering.
HDMP-0482 Absolute Maximum Ratings Ta=25 C, except as specified. Operation in excess of any of these conditions may result in permanent damage to this device. Ta refers to the ambient temperature for the board upon which the parametric measurements were taken. Symbol
VCC VIN, LVTTL VIN, HS_IN IO, LVTTL Tstg Tj
Parameters
Supply Voltage LVTTL Input Voltage HS_IN Input Voltage LVTTL Output Voltage Storage Temperature Junction Temperature
Min.
-0.7 -0.7 1.3
Max.
4.0 4.0 VCC 13
Units
V V V mA C C
-65 0
+150 +125
HDMP-0482 Guaranteed Operating Rates, Ta = 0C to +70C, VCC = 3.15V to 3.45V Serial Clock Rate FC (MBd) Min. Max.
1,040 1,080
Serial Clock Rate GE (MBd) Min. Max.
1,240 1,260
HDMP-0482 CDR Reference Clock Requirements, Ta = 0C to +70C, VCC = 3.15V to 3.45V Symbol
f f Ftol Symm
Parameter
Nominal Frequency (Fibre Channel) Nominal Frequency (Gigabit Ethernet) Frequency Tolerance Symmetry (duty cycle)
Min.
Typ.
106.25 125
Max.
Units
MHz MHz
-100 40
100 60
ppm %
7
HDMP-0482 DC Electrical Specifications, Ta = 0C to +70C, VCC = 3.15V to 3.45V Symbol
VIH,LVTTL VIL,LVTTL VOH,LVTTL VOL,LVTTL IIH,LVTTL IIL,LVTTL ICC
Parameter
LVTTL Input High Voltage Range LVTTL Input Low Voltage Range LVTTL Output High Voltage Range, IOH = -400 A LVTTL Output Low Voltage Level, IOL = 1 mA Input High Current (Magnitude), VIN = 2.4 V, VCC = 3.45 V Input Low Current (Magnitude), VIN = 0.4 V, VCC = 3.45 V Total Supply Current, Ta = 25C
Min.
2.0 0 2.2 0
Typ.
Max.
4.0 0.8 3.45 0.6
Units
V V V V A A mA
.003 300 330
40 600 400
HDMP-0482 AC Electrical Specifications, Ta = 0C to +70C, VCC = 3.15V to 3.45V Symbol
tloop tcell tr,LVTTLin tf,LVTTLin trs,HS_OUT tfs,HS_OUT trd,HS_OUT tfd,HS_OUT VIP,HS_IN VOP,HS_OUT
Parameter
Total Loop Latency from FM_NODE[0] to TO_NODE[0] Per Cell Latency from FM_NODE[7] to TO_NODE[0] Input LVTTL Rise Time Requirement, 0.8 V to 2.0 V Input LVTTL Fall Time Requirement, 2.0 V to 0.8 V HS_OUT Single-Ended Rise Time, 20%-80% HS_OUT Single-Ended Rise Time, 20%-80% HS_OUT Differential Rise Time, 20%-80% HS_OUT Differential Rise Time, 20%-80% HS_IN Input Peak to Peak Required Differential Voltage Range HS_OUT Output Pk-Pk Diff. Voltage Range (Z0 = 75, Fig. 9)
Min.
Typ.
2.8 0.5 2 2 200 200 200 200
Max.
4.2 0.8
Units
ns ns ns ns
350 350 350 350 2000 2000
ps ps ps ps mV mV
400 1100
1200 1400
HDMP-0482 Power Dissipation, Ta = 0C to +70C, VCC = 3.15V to 3.45V Symbol
PD
Parameter
Power Dissipation
Unit
mW
Typ.
1090
Max.
1380
HDMP-0482 Output Jitter Characteristics, Ta = 0C to +70C, VCC = 3.15V to 3.45V Symbol
RJ DJ
Parameter
Random Jitter at TO_NODE pins (1 sigma rms) Deterministic Jitter at TO_NODE pins (pk-pk)
Unit
ps ps
Typ.
5 24
Max.
Please refer to Figures 6 and 7 for jitter measurement setup information.
HDMP-0482 Locking Characteristics, Ta = 0C to +70C, VCC = 3.15V to 3.45V Parameter
Bit Sync Time (phase lock) Frequency Lock at Powerup
Unit
bits s
Max.
2500 500
8
Figure 5. Eye Diagram of TO_NODE[1] High Speed Differential Output. Note: Measurement taken with a 27-1 PRBS input to FM_NODE[0].
2
HDMP-0482
+/- FM_NODE[0] Bias Tee BYPASS[0]BYPASS[1:4]N/C 1 K REFCLK +/- TO_NODE[0] 1.4V
HP70841B Pattern Generator
+/- Data
K28.7
Clock
1062.5 MHz 106.25 MHz
2
HP 70311A Clock Source
1/10 Ch 1/2 106.25 MHz
HP 83480A Digital Trigger Communication Analyzer
Figure 6. Setup for Measurement of Random Jitter.
2
HDMP-0482
+/- FM_NODE[0] Bias Tee BYPASS[0]BYPASS[1:4]N/C 1 K REFCLK +/- TO_NODE[0] 1.4V
HP70841B Pattern Generator
+/- Data
+K28.5
-K28.5
Clock
1062.5 MHz 106.25 MHz
2
HP 70311A Clock Source
1/10 Ch 1/2
106.25 MHz
HP 83480A Digital Trigger 1/10 Communication 53.125 MHz Analyzer
Figure 7. Setup for Measurement of Deterministic Jitter.
9
O-LVTTL
Vcc Vcc
I-LVTTL
Vcc
Vbb 1.4V
ESD Protection
GND
ESD Protection GND
GND
Figure 8. O_LVTTL and I_LVTTL Simplified Circuit Schematic.
HS_OUT
VCCHS VCC VCC VCC 75 Ohms
HS_IN
+ - + -
TO_NODE[n]+
ZO = 75
FM_NODE[n]+ 0.01 F
2 * ZO = 150 ZO = 75 TO_NODE[n]0.01 F FM_NODE[n]-
ESD Protection
GND
GND
ESD Protection
GND
GND
Figure 9. HS_OUT and HS_IN Simplified Circuit Schematic. Note: FM_NODE[n] inputs should never be connected to ground as permanent damage to the device may result.
10
Package Information
HDMP-0482 Thermal Characteristics, TC = 0C to 85C, VCC = 3.15V to 3.45V Symbol
jc
Parameter
Thermal Resistance, Junction to Case
Unit
C/W
Typ.
9.5
Max.
--
Note: Based on independent testing by Agilent. ja for these devices is 39.4C/W for the HDMP-0482. ja is measured on a standard 3x3" FR4 PCB in a still air environment. To determine the actual junction temperature in a given application, use the following equation: Tj = TC + (jc x PD), where TC is the case temperature measured on the top center of the package, and PD is the power being dissipated.
Item
Package Material Lead Finish Material Lead Finish Thickness Lead Skew Lead Coplanarity (Seating Plane Method)
Details
Plastic 85% Tin, 15% Lead 300 - 800 micro-inches 0.20 mm max. 0.10 mm max.
PIN #1 ID
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 HDMP-0482 41 8 40 9 TOP VIEW 39 10 38 11 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
E1
E
c b D1 e D A2 L
G
A
Figure 10. HDMP-0482 Package Drawing.
A1
Mechanical Dimensions of HDMP-0482 Dimensional Parameter (in millmeters) HDMP-0482 Tolerance D1/E1 14.00 0.10 D/E 17.20 0.25 b 0.35 0.05 e 0.80 Basic L 0.88 +0.15/ -0.10 c 0.17 Max G 0.25 Gage Plane A2 2.00 +0.10/ -0.05 A1 0.25 Max A 2.35 Max
11
VCC
GND
VCC
VCC GND VCC GND CPLL1 CPLL0
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
GND
VCC
VCC
HDMP-0482
GND
VCC
GND
VCC
Figure 11. Recommended Power Supply Filtering. Capacitors = 0.1 F, Resistor = 10.
www.agilent.com/semiconductors
For product information and a complete list of distributors, please go to our web site. For technical assistance call: Americas/Canada: +1 (800) 235-0312 or (916) 788-6763 Europe: +49 (0) 6441 92460 China: 10800 650 0017 Hong Kong: (65) 6756 2394 India, Australia, New Zealand: (65) 6755 1939 Japan: (+81 3) 3335-8152(Domestic/International), or 0120-61-1280(Domestic Only) Korea: (65) 6755 1989 Singapore, Malaysia, Vietnam, Thailand, Philippines, Indonesia: (65) 6755 2044 Taiwan: (65) 6755 1843 Data subject to change. Copyright (c) 2003 Agilent Technologies, Inc. Obsoletes 5988-7140EN June 16, 2003 5988-9758EN
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